The present invention is generally related to testing and diagnosing integrated circuits and, more particularly, to testing and diagnosing alternating current scan chain defects and localizing these defects to a particular shift register latch or associated clock tree.
Integrated circuit technology typically utilizes scan based design methodologies and techniques in order to facilitate design, testing, and diagnostic procedures. The scan based design methodology typically reconfigures sequential logic into combinational logic blocks which are interconnected by shift register latches. Typical alternating current (AC) scan design tests the operation of the shift register latches by serially loading and unloading predetermined bit patterns through the shift register latches. The serial output bit patterns are compared to the input patterns to identify faulty latches.
Current scan based designs typically use scan chains to detect AC defects. However, these scan chains are typically tested through the application of external inputs. Presently, no AC scan chain configurations have utilized built-in self test features or on-board clock support.
This invention is directed to an apparatus for performing AC scan chain built-in self test and diagnostics of an integrated circuit. The apparatus includes a reconfigurable linear feedback shift register (LFSR) having an input and a plurality of output lines. The LFSR generates a bit pattern. A plurality of scan chain latches interconnect to the LFSR, and each scan chain latch serially receives at a respective input the bit pattern output by the LFSR. Each scan chain latch propagates the bit pattern from the respective input to a respective output of each scan chain latch. A multiple input signature register (MISR) receives the bit patterns output by the respective scan chain latches, and generates a signature in accordance with the bit patterns input from the scan chain latches. A comparison circuit compares the signature with an expected signature based upon the pattern input to the plurality of scan chain latches. A controller reconfigures the LFSR to vary bit patterns output by the LFSR and varies the timing sequence of the LFSR, the plurality of scan chain latches, the MISR, and the comparison circuit. When the signature is equal to the expected signature, the scan chain latches are functioning correctly.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.